Reliability in semiconductor circuits is an important aspect of chip design, especially with the increasing complexity of the circuits and the increased density of the silicon on which the circuits reside. Connections to IC inputs, outputs, and power are susceptible to electrostatic discharge (ESD) events that can damage internal components. Fundamentally, an ESD event is a short discharge of electric energy caused by the sudden release of an electrostatic build-up of electrical charge. If ESD-induced currents flow suddenly and strongly through electronic components, the high currents can literally melt the carefully formed layers of an IC. A chip is particularly susceptible to ESD when it is not mounted into a larger circuit (e.g., mounted onto a printed circuit board). ESD protection is therefore particularly important in maintaining the reliability of semiconductor products, and commercial ICs are generally expected to sustain without damage an ESD event in excess of 2000 volts, which is often denoted as the human-body-model ESD voltage.
Semiconductor devices are becoming increasingly complex, and at the same time the devices' circuitry is becoming smaller and more crowded on the devices to accommodate the new and complex functions. The decreased size and spacing of the interconnections and internal circuit elements, along with the increasing use of multiple input voltage levels, increases the devices' susceptibility to ESD events occurring on the devices' power supply lines. An additional challenge is to protect the devices' internal circuitry from the ESD voltages and currents that are borne in by the ICs' address, data, and control lines.
Due to the difference of the voltage levels between them, the power lines and power pins of an IC are usually electrically isolated from each other, such that the internal power supplies are derived from the external supplies but are often of different voltages. Such isolation, however, may make for devices that are more susceptible to ESD damage in the devices' interface circuits, even though there may be suitable ESD protection circuits placed around the input and output pads of the IC. Examples of prior-art ESD control approaches are disclosed in the following references: N. Maene, et al., On Chip Electrostatic Discharge Protections for Inputs, Outputs, and Supplies of CMOS Circuits, 1992 PROC. EOS/ESD SYMP. 228; M. D. Ker and T. L. Yu, ESD Protection to Overcome Internal Gate-Oxide Damage on Digital-Analog Interface of Mixed-Mode CMOS IC's, 36 J. MICROELECTRONICS & RELIABILITY 1727 (1996); M. D. Ker, et al., Whole-Chip ESD Protection for CMOS VLSI/ULSI with Multiple Power Pins, PROC. IEEE INT'L INTEGRATED RELIABILITY WORKSHOP 124 (Oct. 16–19, 1994); M. D. Ker, Whole-Chip ESD Protection Scheme for CMOS Mixed-Mode IC's in Deep-Submicron CMOS Technology, PROC. IEEE CUSTOM INTEGRATED CIRCUITS CONF. 31, Santa Clara, Calif., USA, (May 5–8, 1997).
ESD protection circuits are generally more robust in their design than other circuits on a semiconductor device. An ESD circuit will typically redirect ESD voltage and current to an alternate path that is better able to conduct the ESD current and therefore withstand the stresses of the ESD event while protecting the other circuits. In general, ESD protection circuits are located near the device interconnect pads. There are many known configurations of ESD protection circuits. Specific novel implementations of gate-driven clamp circuits are discussed in this application. Some prior-art gate-driven clamp circuits are described in: U.S. Pat. No. 4,855,620 (C. Duvvury et al.); U.S. Pat. No. 5,086,365 (C. D. Lien); C. Duvvury et al., Dynamic Gate Coupling Of NMOS for Efficient Output ESD Protection, 1992 PROC. IRPS. 141; C. Duvvury et al., Achieving Uniform NMOS Device Power Distribution For Submicron ESD Reliability, 1992 TECH. DIG IEDM. 131; Ming-Dou Ker et al, EOS/ESD Reliability of Deep Sub-Micron NMOS Protection Devices, 1995 PROC. OF IRPS 284; S. Ramaswamy et al., Capacitor-Coupled ESD Protection Circuit for Deep-Submicron Low-Voltage CMOS ASIC, 4 IEEE TRANS. VLSI Sys. 307 (Sep. 1996); U.S. Pat. No. 5,631,793 (M. D. Ker et al.).
Clamp circuits work during ESD events to provide a current path from the input pad or power supply to the substrate bias voltage supply, VSS, which is normally ground, or to another circuit element that is equipped to absorb the ESD current. In a conventional power supply clamp circuit, the power supply line is routed to ground through a clamp transistors that is biased to be “off” during normal circuit operation. When a voltage in excess of the maximum allowed voltage on a power supply line is detected by the ESD protection circuit, the clamp transistor will turn “on,” thereby shunting the induced ESD potential to ground. Coupled resistor-capacitor circuits (“RC circuits”) may also be used at power supply inputs to absorb transient power spikes from ESD events. Examples of such circuits are further described in the following references: C. Duvvury et al., Dynamic Gate Coupling of NMOS for Efficient Output ESD Protection, 1992 PROC. OF IRPS 141; C. Duvvury et al., Achieving Uniform NMOS Device Power Distribution For Submicron ESD Reliability, 1992 TECH. DIG. 131; S. Ramaswamy et al., EOS/ESD Reliability of Deep Sub-Micron NMOS Protection Devices, 1995 PROC. IRPS. 284.
As mentioned above, chip designs sometimes support multiple power levels, with for example one power level provided for internal or core circuitry, and with another power level provided for external circuitry. In these circumstances, the external circuitry typically has a voltage level above the internal or core circuitry of the chip designs. For example, the semiconductor technology for one chip design may use 1.8 or 2.5 volts internally, which yields other advantages such as reduced component size and power conservation. The chip's external interface, however, may need to be compatible to a 3.3 volt external voltage, which requires that the chip's external interface accept and, depending on application, drive, 3.3 volt interfaces.
Multiple power-level designs, however, can pose ESD protection challenges, as is detailed by Ming-Dou Ker & Chien-Hui Chuang, Electrostatic Discharge Protection for Mixed-Voltage CMOS I/O Buffers, 37 IEEE J. SOLID-STATE CIRCUITS 1046 (2002). The present application describes an architecture that provides a robust ESD protection method without encountering the difficulties previously associated with the described mixed-voltage circuits.